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VLSI PROJECTS LIST

 

    VLSI  
S.No. PROJECT CODE PROJECT TITLE SYNOPSIS
1 PVLS01 ALGEBRAIC INTEGER-BASED EXACT COMPUTATION Abstract
2 PVLS02 AN EFFICIENT VLSI ARCHITECTURE FOR LIFTING-BASED DISCRETE WAVELET TRANSFORM Abstract
3 PVLS03 AREA-EFFICIENT PARALLEL FIR DIGITAL FILTER STRUCTURES FOR SYMMETRIC CONVOLUTIONS BASED ON FAST FIR ALGORITHM Abstract
4 PVLS04 VLSI ARCHITECTURE FOR ARITHMETIC CODER USED IN SPIHT Abstract
5 PVLS05 EFFICIENT MODULO 2n+1 MULTIPLIERS Abstract
6 PVLS06 4-BIT SFQ MULTIPLIER BASED ON BOOTH ENCODER Abstract
7 PVLS07 CONSTRUCTION OF OPTIMUM COMPOSITE FIELD ARCHITECTURE FOR COMPACT HIGH-THROUGHPUT AES S-BOXES Abstract
8 PVLS08 DESIGN OF DISCRETE-VALUED LINEAR PHASEFIR FILTERS IN CASCADE FORM Abstract
9 PVLS09 DESIGN OF FIXED-WIDTH MULTIPLIERS WITH LINEAR COMPENSATION FUNCTION Abstract
10 PVLS10 EFFICIENT AND HIGH-PERFORMANCE PARALLEL HARDWARE ARCHITECTURES FOR THE AES-GCM Abstract
11 PVLS11 HIERARCHICAL DESIGN OF AN APPLICATION-SPECIFIC INSTRUCTION SET PROCESSOR FOR HIGH-THROUGHPUT AND SCALABLE FFT PROCESSING Abstract
12 PVLS12 HIGH-THROUGHPUT INTERPOLATOR ARCHITECTURE FOR LOW-COMPLEXITY CHASE DECODING OF RS CODES Abstract
13 PVLS13 INVESTIGATING THE IMPACT OF LOGIC AND CIRCUIT IMPLEMENTATION ON FULL ADDER PERFORMANCE (MICROWIND) Abstract
14 PVLS14 LOW-POWER AND AREA-EFFICIENT CARRY SELECT ADDER Abstract
15 PVLS15 TOEPLITZ MATRIX APPROACH FOR BINARY FIELD MULTIPLICATION USING QUADRINOMIALS Abstract
16 PVLS16 DESIGN OF AN ERROR DETECTION AND DATA RECOVERY ARCHITECTURE FOR MOTION ESTIMATION TESTING APPLICATIONS Abstract
17 PVLS17 ROBUST SECURE SCAN DESIGN AGAINST SCAN-BASED DIFFERENTIAL CRYPTANALYSIS Abstract
18 PVLS18 EFFICIENT AES IMPLEMENTATIONS FOR ARM BASED PLATFORMS Abstract
19 PVLS19 SOFT-ERROR-RESILIENT FPGAS USING BUILT-IN 2-D HAMMING PRODUCT CODE Abstract
20 PVLS20 HARDWARE ACCELERATION OF OPENSSL CRYPTOGRAPHIC FUNCTIONS FOR HIGH-PERFORMANCE INTERNET SECURITY Abstract
21 PVLS21 PERIOD EXTENSION AND RANDOMNESS ENHANCEMENT USINGHIGH-THROUGHPUT RESEEDING-MIXING PRNG Abstract
22 PVLS22 TESTABLE PATH SELECTION AND GROUPING FOR FASTER THAN AT-SPEED TESTING Abstract
23 PVLS23 VLSI DESIGN OF AN SVM LEARNING CORE ON SEQUENTIAL Abstract
24 PVLS24 MINIMAL OPTIMIZATION ALGORITHM Abstract
25 PVLS25 ANALOG IMPLEMENTATION OF A NOVEL RESISTIVE-TYPE SIGMOIDAL NEURON (MICROWIND) Abstract
26 PVLS26 ADAPTIVE KEEPER DESIGN FOR DYNAMIC LOGIC CIRCUITS USING RATE SENSING TECHNIQUE(MICROWIND) Abstract
27 PVLS27 ACCURATE TIMING AND NOISE ANALYSIS OF COMBINATIONAL AND SEQUENTIAL LOGIC CELLS USING CURRENT SOURCE MODELING VOLTAGE SCALING DEVICES Abstract
28 PVLS28 MEMORY EFFICIENT MODULAR VLSI ARCHITECTURE FOR HIGHTHROUGHPUT AND LOW-LATENCY IMPLEMENTATION OF MULTILEVEL LIFTING 2-D DWT Abstract
29 PVLS29 INPUT-FEATURE CORRELATED ASYNCHRONOUS ANALOG TO INFORMATION CONVERTER FOR ECG MONITORING Abstract
30 PVLS30 HIGH-THROUGHPUT SOFT-OUTPUT MIMO DETECTOR BASED ON PATH-PRESERVING TRELLIS-SEARCH ALGORITHM Abstract
31 PVLS31 LOW-SWING DIFFERENTIAL CONDITIONAL CAPTURING FLIP-FLOP FOR LC RESONANT CLOCK DISTRIBUTION NETWORKS Abstract
32 PVLS32 JITTER ANALYSIS OF POLYPHASE FILTER-BASED MULTIPHASE CLOCK IN FREQUENCY MULTIPLIER Abstract
33 PVLS33 LOW POWER AND LOW COMPLEXITY COMPRESSOR FOR VIDEO CAPSULE ENDOSCOPY Abstract
34 PVLS34 A 4T LOW-POWER LINEAR-OUTPUT CURRENT-MEDIATED CMOS IMAGE SENSOR Abstract